1. Field of the Invention
This invention relates to current sampling methods and circuits, particularly but not exclusively for capturing output signals from sensors which have a current output.
2. Description of the Related Art
In a number of sensing applications, the sensing devices (for example diodes or transistors) generate an output current which depends on the parameter to be sensed. The range of applications in which current sensors can be used is enormous, and this invention can be applied to any such application. For example, the parameter to be sensed can be a light level in the case of a photosensor or a temperature in the case of a temperature sensor. The sensor will measure a physical property such as light, temperature, strain or other forces.
The output current of a sensor will often be very small, and it is advantageous to convert the signal to a more robust form close to the sensor in order to preserve the quality of the signal, particularly the signal to noise ratio. Sampling of the current is required in the case where the signal changes over time or when the output of several sensors is multiplexed together as is the case for an array of sensors.
Conventional current sampling circuits can be slow to acquire new signals, particularly when the currents are small.
FIG. 1 shows a known simple sampling circuit. The current to be sampled may for example comprise a photocurrent, and is represented by a current source 10. The current is drawn through a p-type drive transistor T1p, which has a capacitor C1 connected between its source and gate. This capacitor can thus store the gate-source voltage corresponding to the current being sampled.
The circuit has a first switch S1 (with timing clk1) between the gate and drain of the transistor T1p for turning the transistor on so that it can supply the current being sampled. A second switch S2 (with timing clk2) couples the transistor T1p to the sensor, and a third switch S3 (with timing clk3) couples the transistor T1p to the output of the sampling circuit.
As shown in FIG. 2, during a sampling phase S the switches S1 and S2 are closed and the switch S3 is open. The current to be sampled, the photocurrent in this example, is drawn through the transistor T1p. The voltage present on the gate and the drain of T1p settles at a value which produces a drain current in T1p which is equal to the photocurrent. This voltage becomes stored across the capacitor C1. During a holding phase H the switches S1 and S2 are opened and the switch S3 is closed. The gate-source voltage of T1p is maintained by C1 and therefore the sampled photocurrent is available at the output of the circuit.
The time required to sample the current is proportional to (C1+Cd)/gm1 where Cd is the capacitance of the sensor (i.e. the photodiode) and gm1 is the transconductance of the transistor T1p. When the current to be measured is small, the transistor T1p will be operating in the sub-threshold region. In this region, the value of gm1 is proportional to the drain current Id1. Therefore when the current to be sampled is low the settling time is extended.
The settling time can be reduced using the circuit shown in FIG. 3.
The p-type transistor T1p is replaced by an n-type transistor T1n and an inverting amplifier 20 is connected between the source of the transistor T1n and the gate. The storage capacitor C1 is again between the source and gate, as the n-type transistor has its drain connected to the high voltage line VDD. With this arrangement, the settling time is now proportional to (C1+Cd)/(A·gm1), where A is the gain of the inverting amplifier 20. This reduces the settling time of the circuit by increasing the effective value of the transconductance of T1n. 
A switch S4 (with timing clk4) opens or closes the amplifier feedback loop, and a switch S5 (with timing clk5) can reset the amplifier.
As shown in FIG. 4, during the sampling phase S the switches S2 and S4 are closed, while the S3 and S5 are open, so that the gate of T1 sees an amplified version of the voltage at its source. The gate source voltage Vgs of T1n required to produce a drain current equal to the photocurrent gets stored across C1. During the holding phase H the switches S4 and S2 are open, whereas S3 and S5 are closed. T1n provides the sampled current as output of the circuit. The amplifier sits around its threshold with its input and output connected together, thus ensuring that the voltage node associated with the sensor (in this example the cathode of the photodiode) is kept fairly constant.
The capacitor C1 in FIG. 3 is connected between the input and the output of the inverting amplifier 20 during the sampling phase S. Due to the Miller effect, the effective value of C1 is increased, since the inverting amplifier 20 sees an equivalent capacitance A.C1 between its input and ground. This equivalent capacitor is in parallel with Cd and tends to make the circuit slow.
The circuit in FIG. 3 is also limited by the current that needs to be sampled. That current fixes a gate source voltage for T1n that needs to be built up on the storage capacitor C1. When sampling for example 350 pA, the gate source voltage needed is approximately 700 mV, which corresponds to a particular operating point of the inverting amplifier.
FIG. 5 shows a plot of the gain of an inverting amplifier as a function of Vout-Vin, which in the sampling phase is the gate source voltage of T1n. It can be seen that the operating point of the inverting amplifier, set by the gate source voltage of T1n, will be different from the voltage at which the gain is maximum (in absolute value). In other words, the amplifier 20 is not biased to its optimum operating point. This shows a fundamental limitation of the approach shown in FIG. 3.